Subtract the following binary numbers by the 2's and 1's complement method. 10110-1011
[3 marks]Encode data bits 1011 into the 7-bit even parity Hamming code. Find and correct error from 7-bit hamming code given below.
[4 marks]Explain TTL and CMOS realization of AND and OR gate.
[7 marks]For a two input AND & OR gate, Determine its output waveform in relations to input waveform A & B. Input Ahas frequency 2Hz with duty cycle 50% and Input Bhas frequency 1Hz with duty cycle 70%.
[3 marks]Explain EX-OR and EX-NOR gate using its truth table, Symbol, and logic diagram.
[4 marks]Reduce the expression f=∑m(1,4,7,10,13)+d(5,14,15) using k-map and implement the minimal expression in universal logic.
[7 marks]Find the minimal expression for f = ∏M(2,8,9,10,11,12,14) using tabular method.
[7 marks]Reduce the Boolean Expression: f = AB+AC +ABC(AB+C).
[3 marks]Design 4-input priority encoder.
[4 marks]Design Half adder and Half subtractor using universal logic.
[7 marks]Draw logic diagram of 3-8 line decoder.
[3 marks]Find out Minterms and Maxterms for Boolean expression: f = A(A +B)(A+B +C).
[4 marks]Implement the logic function F=∑m(0,1,2,3,4,10,11,14,15) using a 16:1 MUX and 8:1 MUX.
[7 marks]Explain 1-bit Magnitude comparator with logic diagram.
[3 marks]Design full adder using PAL circuit.
[4 marks]Design a 4-bit Binary to Gray Code converter with logic diagram.
[7 marks]Write comparison of programmable logic devices.
[3 marks]Design full subtractor using PLA circuit.
[4 marks]Explain design of a synchronous 3-bit Up-Down counter using J-Kflip-flops.
[7 marks]Write comparison between synchronous and asynchronous sequential circuits.
[3 marks]Describe master-slave pulse triggered D-flip-flop.
[4 marks]Explain edge-triggered J-Kflip-flop and T-flip-flop.
[7 marks]Write excitation tables of S-R, J-K, D, and Tflip-flop.
[3 marks]Describe Serial In, Parallel Out shift register.
[4 marks]Design and explain Asynchronous two bit ripple up and down counter using negative edge triggered J-Kflip-flops.
[7 marks]