Explain difference between combinational logic and sequential logic.
[3 marks]Explain basic architecture of computer.
[4 marks]Explain D-Latch and D-Flip flop in detail.
[7 marks]Explain data attributes with example.
[4 marks]Explain difference between Signal and Variable.
[3 marks]Explain Finite state machines in detail.
[7 marks]Explain top-down design approch in detail.
[7 marks]Explain association connectivity in port map.
[3 marks]Explain WHILE-LOOP and FOR-LOOP statement in VHDL
[4 marks]Explain data flow modeling with example.
[7 marks]Explain signal attributes with example.
[3 marks]Describe inertial delay model in brief.
[4 marks]Explain behavioral modeling with example.
[7 marks]Write a VHDL code for half adder.
[3 marks]Write a VHDL code to implement 4-bit counter.
[4 marks]Explain predefined operators used in VHDL.
[7 marks]Explain IF statement used in VHDL
[3 marks]Describe transport delay model in brief.
[4 marks]Write a VHDL code for 8 X 1 Multiplexer.
[7 marks]Describe utility of LUT block in FPGA.
[3 marks]Explain use of CLB or LAB in FPGA.
[4 marks]Explain architecture of CPLD.
[7 marks]Discuss use of PAL blocks in CPLD.
[3 marks]Explain use of PLDA for generating control signals for Power electronics application.
[4 marks]Explain architecture of FPGA.
[7 marks]