Implement AND, OR, EX-OR gates using NAND & NOR gates.
[7 marks]List out various logic families. Also list characteristics of digital IC.
[3 marks]State and prove De-Morgan’s theorems using truth-tables.
[4 marks]Design a Combinational circuit that convert BCD to Excess 3 code converter.
[7 marks]Reduce the expression F = x’y’z +yz+ xz
[3 marks]Convert the decimal Number 330.5 to base 4 and base 8.
[4 marks]Design a Combinational circuit that convert Binary to BCD code converter.
[7 marks]Minimize following Boolean function using K-map: F(A,B,C,D) = Σ m(1, 5, 6, 12, 13, 14) + d(2, 4)
[4 marks]Minimize following Boolean function using K-map: Y(A,B,C,D) = Σ m(0, 1, 3, 5,6, 7, 10, 13,14, 15)
[3 marks]Explain 4 – bit parallel adder with diagram.
[4 marks]Design 2 - Bit Magnitude Comparator.
[7 marks]Design D FF using SR FF. Write truth table of D FF.
[3 marks]Design 3-bit even parity generator circuit.
[7 marks]Explain Look-ahead Carry generator
[4 marks]Compare static RAM and dynamic RAM.
[3 marks]Explain JK flip flop with its characteristic table and excitation table.
[4 marks]Write a brief note on race around condition and its solution. Draw & explain the logic diagram of master-slave JK flip-flop.
[7 marks]Explain the types of ROM.
[3 marks]Design a Synchronous counter with the following binary sequence: 0, 1, 3, 4,5, 7 and repeat. Use T – flip-flops
[7 marks]Describe operation of D/Aconverter with binary-weighted resisters
[7 marks]Explain R-2R ladder type D/Aconverter
[4 marks]Acombinational circuit is defined by the function F1 (A, B, C,) = Σ m (0,1,3,4) F2 (A, B, C,) = Σ m (1.2.3,4,5) Implement the circuit with a PLA having 3 inputs, 3 product term & 2 outputs.
[7 marks]Explain the working of SISO shift register.
[3 marks]Explain the specification of D/Aconverter
[4 marks]Explain the working of a Counter.
[3 marks]