VLSI Technology and Design — Summer 2025

Write 3 main differences of FPGA and CPLD.

Draw Ychart and Flow chart of VLSI Design Flow.

Explain Fabrication of n-MOSFET with neat sketch.

Define concept of Regularity, Modularity and Locality in VLSI Design.

Enlist different packaging technologies and explain any one.

Explain different regions of MOS system under external bias with energy band diagram.

Compare Full custom, Semi custom and Fully Programmable VLSI design style.

Enlist different types of MOSFET capacitance.

Draw idea and practical inverter voltage transfer characteristics and define all critical voltages and noise margin.

Derive drain current of MOSFET using gradual channel approximate.

What are the different small geometry effects?

Compare different load inverters.

Explain MOSFET Scaling and compare it.

How will you calculate propagation delay times using average current method?

Design resistive load inverter: Given V = 5 V, k ' = 30 uA/V2, and V = 1 V, dd To with V = 0.2 V. Specifically, determine the (W/L) ratio of the driver transistor OL and the value of the load resistor RL that achieve the required V OL..

Draw CMOS inverter. Consider a CMOS inverter with the following parameters: V = 0.6 V, V = - 0.7 V ,K = 200 uA/V2, K = 80 uA/V2 and V = 3.3 V. Ton Top n p DD Find NM for a given inverter. L

Define rise time, fall time and propagation delay time of CMOS inverter.

Derive switching power dissipation equation of CMOS inverter with idea step input.

Draw i/p and o/p waveform during high to low transition of o/p for CMOS inverter and derive expression for t Using differential equation method. PHL.1

Implement the following Boolean function using CMOS inverter F=[(C+D+E)(B+A)]’

Implement 2 inputs NOR and NAND gates using depletion load inverter.

Explain CMOS Transmission gate

Implement NOR gate based SR latch using CMOS inverter.

Draw CMOS implementation of Dlatch with two inverter and two CMOS TG gates.

Draw ASIC design flow chart and write HDL program to implement 4x1 multiplexer using verilog hardware description language.