VLSI Technology and Design — Winter 2025

Write VHDL program for 1-bit full adder.

Design CMOS SR latch circuit based on NOR gate.

Explain Fabrication of n-MOSFET with neat sketch.

Enlist different types of MOSFET capacitance.

Compare different load inverters.

Draw i/p and o/p waveform during high to low transition of o/p for CMOS inverter and derive expression for t using differential equation method. PHL

Explain interconnect delay analysis using Elmore Delay model.

Why is the size of PMOS transistor chosen to be 2.5 times of an NMOS transistor?

Construct Dlatch using CMOS inverters and Transmission Gates.

Derive MOSFET current -voltage characteristics using gradual channel approximation.

Derive switching power dissipation equation of CMOS inverter with idea step input.

Draw CMOS ring oscillator and its out waveform. Write generated frequency equation.

Explain MOS System under External Bias with neat sketch of cross sectional view and energy band diagram and derive depletion region depth equation.

Compare constant field and constant voltage scaling.

Draw resistive load inverter. Derive Vand Vcritical voltages equation of OL IL resistive load inverter.

Write a short note on CMOS Transmission gate.

Implement following Boolean expression using CMOS inverter Z= (A(D+E)+BC)’ Page 1 of

Draw CMOS inverter with leads name of pMOS and nMOS transistors. Derive V IL critical Voltage equation of CMOS inverter

Draw ASIC design flow chart and write HDL program to implement 4x1 multiplexer using verilog hardware description language.

Draw VLSI design flow Ychart.

Implement 2 inputs NOR and NAND gates using depletion load inverter.

Draw CMOS implementation of Dlatch with two inverter and two CMOS TG gates.

Define Concept of Regularity, Modularity, and Locality.

Explain ASIC design flow.

Derive the equation for propagation delay of output signal during high to low transition of output of CMOS inverter circuit with Cas load capacitance. load Page 2 of