Define Concept of Regularity, Modularity, and Locality.
[3 marks]Compare full-custom, semi-custom and programmable VLSI design style.
[4 marks]Explain nMOS fabrication steps using neat sketch.
[7 marks]Draw VLSI design flow Ychart.
[3 marks]Draw voltage transfer characteristics of ideal and practical inverter and define V , V , V , V , NM and NM . IL IH OL OH L H
[4 marks]Derive MOSFET current -voltage characteristics using gradual channel approximation.
[7 marks]Explain MOS System under External Bias with neat sketch of cross sectional view and energy band diagram and derive depletion region depth equation.
[7 marks]What is the need of Scaling? Compare constant field and constant voltage scaling.
[3 marks]Draw resistive load inverter. Derive Vand Vcritical voltages OL IL equation of resistive load inverter.
[4 marks]Consider resistive-load inverter with R = 200 kΩ. The enhancement- L type nMOS driver transistor has the following parameters V = 5 V, DD V = 0.8V μnCox = 20 µA/V2 , W/L= 2. Determine V , Vand TO OL IL NM . L
[7 marks]Write VHDL program for 1-bit full adder.
[3 marks]Draw CMOS inverter with leads name of pMOS and nMOS transistors. Derive Vcritical Voltage equation of CMOS inverter IL
[4 marks]Consider a CMOS inverter circuit with the following parameters: V DD =3.3V, V =0.6 V, V = -0.7 V, kn = 200 µA/V2 , kp = 80 μA/V2 TON TOP , find the NM L
[7 marks]Implement following Boolean expression using CMOS inverter. Z= (A(D+E)+BC)’
[3 marks]Realize following Boolean logic equation using Transmission Gate (TG). F = XY+ X’Z’+XY’Z
[4 marks]Derive the equation for propagation delay of output signal during high to low transition of output of CMOS inverter circuit with Cload as load capacitance. OR1
[7 marks]Draw CMOS ring oscillator and its out waveform. Write generated frequency equation.
[3 marks]Construct d latch using CMOS inverters and Transmission Gates.
[4 marks]Explain interconnect delay analysis using Elmore Delay model.
[7 marks]Derive switching power dissipation equation of CMOS inverter with idea step input.
[3 marks]Design CMOS SR latch circuit based on NOR gate.
[4 marks]Explain MOSFET capacitance in detail.
[7 marks]Why is the size of PMOS transistor chosen to be 2.5 times of an NMOS transistor?
[3 marks]Explain ASIC design flow.
[4 marks]Write a short note on CMOS Transmission gate.
[7 marks]