Describe: (1) Regularity (2) Modularity (3) Locality
[3 marks]Differentiate Full Custom and Semi Custom Design flow
[4 marks]Describe VLSI Design Flow.
[7 marks]Describe process of photo lithography with example.
[3 marks]Describe FPGA Architecture.
[4 marks]Sketch PMOS fabrication steps
[7 marks]Describe device isolation techniques with example.
Derive equation for depletion depth for inversion region of two terminal MOS structure.
[3 marks]Sketch Resistive load NMOS inverter circuit and its VTC. Derive equation of V OL
[4 marks]Describe Gradual Channel Approximation and Derive equation for drain current.
[7 marks]For NMOS transistor, gate voltage is 2v, drain voltage is 5v, source is connected to ground and threshold voltage is 1v. Find operating region of NMOS and drain current. (Kn = 60 µA/V2)
[3 marks]Sketch CMOS inveter circuit and its VTC. Describe various regions of VTC. Derive equation for Vth.
[4 marks]What is Scaling? Describe voltage scaling and derive necessary parameter.
[7 marks] Define: , with necessary diagram. PHL PLH, rise
[3 marks]Sketch and Describe D-Latch circuit using CMOS-Transmission Gate(TG).
[4 marks]Why does NMOS pass strong logic-0 and weak logic-1?
[7 marks]Describe CMOS ring oscillator
[3 marks]Sketch static CMOS circuit for following Boolean equation. F1 = X’Y + XY’ F2 = AB(C+D)
[4 marks]Describe basic dynamic CMOS logic concept.
[7 marks]Describe FinFET Structure with neat diagram.
[3 marks]Describe Latch-up problem in IC.
[4 marks]Describe different types of fault.
[7 marks]Compare FinFET and MOSFET.
[3 marks]Describe methods for on-chip clock generation.
[4 marks]Describe Ad-Hoc Testable design technique.
[7 marks]