VLSI Design — Summer 2024

Compare semicustom and Full custom VLSI design style.

Discuss following approaches used to reduce complexity of IC design

Hierarchy ii) Regularity iii) Modularity iv) Locality

Draw and explain various fabrication steps for CMOS inverter with proper notations at each fabrication steps.

Explain MOSFET capacitance in brief.

Derive the drain current equation for MOSFET using Gradual Channel Approximation (GCA)

Find the depletion layer width, depletion region charge and threshold voltage with no substrate bias with the following physical parameters. Physical parameters VSB=0, for silicon gate n channel MOS transistor, with the following parameters: Substrate doping density NA=1.5 x 1016 cm-3, Gate donor doping N = 1018 cm-3, D Gate oxide thickness tox = 400A, Nss = 10 x 1010 cm-3. Consider Boltzmann Constant = 1.38 x10-23 (J/K), Electron charge = 1.6 x 10-19 C, Intrinsic Silicon carrier concentration ni= 1.45 x 1010 cm-3, ε i = 1.035 x 10-12 F/cm S ε = 8.85x10-14 F/cm,0 εox = 0.345 x 10-12 F/cm.

For an enhancement type NMOS transistor has its source terminal connected to ground and 3 Vconnected to ground and 3 Vconnected to the gate. NMOS has V = 2 V , = 0.04 1/V ,  *C =20A/V2, W= 200m and L =10m , V = Tn ox G 3V , V =0.5 Vand 1 V. Calculate Drain Current I D D. Physical constants : Thermal voltage =KT/q = 0.026 volt. Energy Gap of silicon (Si) =E = 1.12 Ev. g Intrinsic Carrier Concentration of silicon=n=1.45x1010cm–3 . i Dielectric constant of vaccume =ε =8.85 x 10-14F/cm. o Dielectric constant of silicon =ε = 11.7 xε F/cm. si o Dielectric constant of silicon dioxide =ε = 3.97 xε F/cm ox o

What is meant by static and dynamic power dissipation?

Define propagation delay and derive the expression for pHL for CMOS inverter. Assume ideal step as an input to CMOS inveter.

Consider a resistive load inverter circuit with V =5 V, Kn’ =10A/V2 DD V =0.8V,RL=400kΩ and W/L=2.Calculate the critical Voltages TO (V ,V ,Vand V ) on the VTC and find the noise margins of the OH OL IL IH circuit.

Draw CMOS inveter. Explain its voltage transfer characteristic. Also explain the NML and NMH noise margins with respect to this transfer characteristic 4.4.13

Draw the inverter circuit with depletion type nMOS load. Mention the operating regions of driver and load transistors for different input voltages. Derive critical voltage points V , V , Vand Vfor OH OL IH IL depletion- load nMOS inverter

Consider a CMOS inverter with the following parameters: VDD=3.3 V, VT0,n= 0.6 V, VT0,p= −0.7 V ,kn= 200 𝜇A/V2 and kp= 160 𝜇A/V2 Calculate the noise margins of the circuit. Consider kR=2.5 Vand VT0,≠|VT0,p| as it is not a symmetric CMOS inverter.

What are the limitations of Dynamic circuits? Discuss the effect of charge sharing and charge leakage in dynamic pass transistor logic.

Two nMOS transistors (M1 and M2) connected in series is shown in Figure 1. The power supply is VDD =3.3 Vand the nMOS threshold V = 0.55 V. Find the output voltage at node b. Consider i) Va = 2.7 V TN and ii) Va = 3V. Figure 1

Explain the Euler path approach to find the optimized stick-diagram for any CMOS logic circuit. Draw the optimized stick-diagram for the following Boolean function (CMOS Logic), F= (A(D+E)+ BC)’. Explain the importance of Euler path approach.

What do you mean by stick diagram? Implement the following Boolean function using stick diagram. Y = (A*(D+E)+B*C)’

Explain the need of Voltage bootstrapping? Derive the mathematical expression for dynamic Voltage bootstrapping circuit.

For the Exclusive OR function , draw with following realization 1. Static CMOS realization 2. Pseudo nMOS gate 3. CMOS Transmission Gate(TG)

Compare FinFET and Planner MOSFET

Draw transistor level circuit diagram of NAND based SR latch using CMOS.2

What is clock-skew? Explain on-chip clock generation and distribution.

Draw and discuss three stage ring oscillator

Implement and Describe CMOS clocked SR flip-flop

What is need of Design of Testability (DFT) in VLSI IC design and explain Built in Self Test (BIST) techniques of DFT