VLSI Design — Winter 2022

What is reliability of the chip? List the 4 major causes for chip reliability problems.

Explain the impact of full-custom and semi-custom VLSI design style on design cycle time and circuit performance.

Explain the process steps for fabrication of n-type MOSFET.

Draw the VTC of resistive load inverter circuit and show the 3 different operating regions of MOSFET of the circuit on it.

What is channel length modulation effect?

Explain the MOS system under external bias for accumulation and inversion region.

Derive the drain current Iequation for n-type MOSFET using gradual D channel approximation.

Elaborate different clock distribution network.

Draw and explain the operation of two input multiplexer using CMOS transmission gates.

Derive the equation of Vand Vfor CMOS inverter. IL IH

What is Latch-up in CMOS chip?

For the function Z = A ( D + E ) + B C . Construct dual pull up graph from04 pull down graph using Dual Graph Concept.

Consider a CMOS Inverter circuit with the following parameters: V = 3.3V, V = 0.6V, V = - 0.7V, k = 400 μA/V2, k =160 μA/V2 . DD TO,n TO,p n p Find the value of V . IL

Explain constant field scaling for MOSFET.

Illustrate the RC delay models for calculation of interconnect delay.

Derive the equation for propagation delay of output signal during high to low transition of output of CMOS inverter circuit with Cas load capacitance. load

Draw the circuit of dynamic D-latch.

What are controllability and observability? Discuss in brief.

Explain the working of clocked NOR based SR latch with gate level circuit and waveform. Draw the AOI based implementation of this circuit.

What are the advantages of FinFET over planner MOSFET?

What is substrate bias effect? For two input depletion load NAND gate, how many MOSFET have this effect?1

How pre-charge and evaluate logic works for dynamic CMOS circuit? Explain with example.

How partition and Mux technique is used to increase the testability of circuits?

Draw and explain the basic structure of FinFET device.

Explain NORA CMOS logic and its advantages.