What is chip reliability? List the four major causes of chip reliability issues.
[3 marks]Explain the channel length modulation effect in n-channel MOSFET operation.
[4 marks]Explain the MOS system under external bias for accumulation and depletion region. r egion.
[7 marks]What is substrate bias effect?
[3 marks]Compare and explain the full custom and semi-custom design style of VLSI.
[4 marks]Draw and explain the basic steps of Local oxidation of Silicon (LOCOS) process.
[7 marks]Explain the process steps for fabrication of n-channel MOSFET.
[7 marks]Explain RC delay models for calculation of interconnect delay.
[3 marks]For depletion load n MOS inverter circuit, derive the equation of V . IL
[4 marks]Consider the CMOS inverter circuit with following parameters: V = DD 3.3V, k =200 μA/V2, k =80 μA/V2, V = 0.6V, V = -0.7V. Calculate n p TO,n TO,p the Vand Von the VTC of the inverter. IL OH
[7 marks]Draw the circuit of 2 input CMOS NAND gate and explain its working with the help of truth table.
[3 marks]Why in symmetrical and ideal CMOS inverter required (W/L)p ≈ 2.5 (W/L)n ? Explain in detail.
[4 marks]Consider a resistive load inverter circuit with V = 5V, k’ =20μA/V2, V DD n TO = 0.8V, R = 200 kΩ and W/L =2. Calculate Vand Von the VTC of L OL IH the inverter.
[7 marks]Explain AOI (AND-OR-INVERT) and OAI (OR-AND-INVERT) circuit categories with example for CMOS logic.
[3 marks]Derive switching power dissipation equation of CMOS inverter.
[4 marks]How logic “1” transfer happens in nMOS pass transistor circuits. Explain with suitable example.
[7 marks]Draw the AOI based implementation of the clocked NOR based SR latch circuit.
[3 marks]Implement XOR function using CMOS TG (Transmission Gates).1
[4 marks]Explain various on chip clock generation circuits and distribution networks.
[7 marks]Draw the CMOS implementation of D-latch.
[3 marks]What is controllability and observability for design for testability (DFT)?
[4 marks]How pre-charge and evaluate logic works for dynamic CMOS circuit? Explain with example.
[7 marks]Compare FinFET and Planner MOSFET.
[3 marks]Explain scan-based techniques for DFT with one example.
[4 marks]Define propagation delay τ and obtain its expression for CMOS inverter PHL circuit.2
[7 marks]