Define concept of : Modularity, Locality and Regularity
[3 marks]Explain accumulation, depletion and inversion of MOS under external bias.
[4 marks]Explain process flow of fabrication of nMOS transistoron p-type silicon.
[7 marks]Explain in short: FPGA
[3 marks]What is transmission gate?
[4 marks]Derive MOSFET current -voltage characteristics using gradual channel approximation.
[7 marks]Measured voltage and current data for a MOSFET are given below: Determine the type of the device and calculate the parameters k , V , and γ. Assume φ = -0.3V. Assume MOSFET n TO F is enhancement type and neglect channel length modulation effect. V (V) V (V) V (V) I (μa) GS DS SB D
[7 marks]Explain noise margin.
[3 marks]Explain rise time and fall time of inverter using diagram.
[4 marks]Consider a resistive load inverter circuit with V = 5V, k ' DD n =20μA/V2, V = 0.8V, R = 200kΩ and W/L =2. Calculate TO L critical voltages (V , V , V , V ) and find the noise margins OL OH IL IH of the circuit.
[7 marks]Explain voltage transfer characteristics of inverter.
[3 marks]Explain propagation delay time for inverter: τ , τ PLH PHL
[4 marks]Explain CMOS inverter and find equation of Vand V . IL IH
[7 marks]Explain different fault types in chip.
[3 marks]Explain two input CMOS NOR gate.
[4 marks]Explain Elmore delay with suitable diagram.
[7 marks]What is latch-up? Write causes of latch- up.
[3 marks]Draw CMOS implementation of XOR function.
[4 marks]Explain CMOS ring oscillator circuit.
[7 marks]Explain Controllability and Observability.
[3 marks]Design CMOS SR latch circuit based on NOR gate.
[4 marks]Explain Domino CMOS logic.
[7 marks]Compare FinFET and Planner MOSFET.
[3 marks]Explain CMOS implementation of D - latch.
[4 marks]Explain voltage bootstrapping.
[7 marks]