Draw CMOS inverter circuit and cross section view of nMOSFET.
[3 marks]Draw voltage transfer characteristics of inverter and define V , V , V , V , NM and NM . IL IH OL OH L H
[4 marks]Derive threshold voltage equation and explain what is substrate bias effect.
[7 marks]Realize following Boolean logic equation using CMOS inverter. Z= (AB+C(D+E))’
[3 marks]Compare Static and Dynamic logic circuit.
[4 marks]Derive drain current using gradual channel approximation.
[7 marks]Draw VTC of CMOS inverter and find operating region of NMOS and PMOS at different input voltage ranges from 0 to Vdd.
[3 marks]Derive Critical voltages Vand Vof CMOS inverter IL IH
[4 marks]Consider a CMOS inverter with the following parameters: VTon = 0.6 V, VTop = - 0.7 V ,Kn’ = 50 uA/V2, Kp’ = 16 uA/V2, (W/L)n = 4, (W/L)p = Calculate the noise margins of this circuit. The power supply voltage is VDD = 3.3 V.
[5 marks]Draw resistive load inverter circuit and its VTC curve.
[3 marks]Derive critical voltages V , V , Vand Vof OH OL IL IH resistive load inverter.
[4 marks]Design resistive load inverter with following parameters: VTon = 0.8 V, Kn’ = 20 uA/V2, (W/L)n = 2, R = 200 L kohm and Vdd=5V. Calculate the noise margins of this circuit.
[7 marks]Draw transistor level circuit diagram of NOR based SR latch using CMOS.
[3 marks]Derive switching power dissipation equation of CMOS inverter with idea step input.
[4 marks]Justify importance of transmission gate. Realize following functions using TG.
[7 marks]F=AB+A’C’+AB’Cand ii) F=AB’ + A’B
[ marks]What is need of domino CMOS logic circuit and draw it’s circuit diagram.1
[3 marks]Explain Ring oscillator
[4 marks]Draw i/p and o/p waveform during high to low transition of o/p for CMOS inverter and derive expression for τ . PHL using differential equation method.
[7 marks]Draw CMOS implementation of Dlatch with two inverters and two CMOS TG gates.
[3 marks]Compare CPLD and FPGA.
[4 marks]Draw and Explain different clock generator and distributor circuits
[7 marks]Compare FinFET and Planner MOSFET
[3 marks]Compare constant voltage and constant filed scaling.
[4 marks]What is need of Design of Testability (DFT) in VLSI IC design and explain Built in Self Test (BIST) techniques of DFT.
[7 marks]