Explain VLSI Design flow using Y-chart
[3 marks]Draw voltage transfer characteristics of inverter and define V , V , IL IH V , V , NM and NM OL OH L H
[4 marks]Derive the drain current equation for MOSFET using Gradual Channel Approximation (GCA).
[7 marks]Compare Semi-custom and Full custom VLSI design style
[3 marks]Realize following Boolean logic equation using CMOS inverter. Z= (AB+C(D+E))’
[4 marks]Explain the band diagram of MOS Structure at surface inversion and derive the expression for threshold voltage.
[7 marks]Explain with net sketch diagram nMOSFET fabrication flow.
[7 marks]Write advantages and disadvantages of dynamic logic circuit.
[3 marks]Draw resistive load inverter. Derive VIL and VIH critical voltage equation of resistive load inverter.
[4 marks]Design a resistive-load inverter with R = 1 kΩ, such that V = 0.6 V. The L OL enhancement-type nMOS driver transistor has the following parameters V DD = 5 .0 V V = 1. V μnCox = 22.0 µA/V2 (a) Determine the required aspect TO ratio, W/L. (b) Determine Vand V . (c) Determine noise margins NM and IL IH L NM . H
[7 marks]Why in symmetrical and ideal CMOS inverter required (W/L)p ≈ 2.5(W/L)n. Justify.
[3 marks]Draw CMOS inverter with leads name of pMOS and nMOS transistors. Derive Vcritical Voltage equation of CMOS inverter IL
[4 marks]Consider a CMOS inverter circuit with the following parameters: V =3.3V, DD V =0.6 V, V = -0.7 V, kn = 200 µA/V2, kp = 80 μA/V2 , find the NM TON TOP L
[7 marks]What is the need of Scaling? Mention the merits and demerits of constant field scaling.
[3 marks]Draw CMOS implementation of Dlatch with two inverters and two CMOS TG gates.
[4 marks]Draw circuit of CMOS two inputs NOR gate. Derive Vof the same. TH
[7 marks]Give comparison between FPGA and CPLD.
[3 marks]Implement following Boolean logic equation using Transmission Gate (TG). Y = AB+ A’C’+AB’C
[4 marks]Explain voltage bootstrapping and derive capacitance ration equation?
[7 marks]Draw block diagram of Built in Self Test (BIST).
[3 marks]Find a equivalent CMOS inverter circuit for simultaneous switching of all inputs, assume that (W/L)p = 15 for all pMOS transistors and (W/L)n = for all nMOS transistors for the following Boolean equation F =[(C+D+E) . (B+A)]’
[10 marks]Write a short note on CMOS Transmission gate.
[7 marks]Compare FinFET and Planner MOSFET.
[3 marks]Draw NAND gate based CMOS SR latch circuit.
[4 marks]Discuss the on-chip clock generation and distribution.
[7 marks]