Testing and Verification — Summer 2023

Calculate number of collapsed faults for two input CMOS NAND Gate.

Define following: 1. Rule of Ten 2. Equivalent faults 3. Fault collapsing 4. Fault

cWovheart aigs eb ridging fault? Explain various bridging fault models.

List down the challenges in VLSI testing.

Define following :1. Delay fault 2. Pattern sensitivity fault 3. Coupling fault 4. Exhaustive testing

Explain testing methodology for transistor faults in two-input CMOS NOR Gate.

Discuss logic levelization algorithm with the help of an example.

Explain scan stitching.

What is mean by scan design rules? Explain scan design rules for combinational feedback loops.

What is Hazard? Explain various types of hazards.

List and explain different level of abstraction in VLSI testing.

Discuss scan configuration and its importance in scan design flow.

Explain deductive fault simulation.

Write down the truth table of AND, OR and NOT gate using ternary logic.

Calculate probability-based measures for 3 input OR gate.

Draw and explain LSSD scan cell design with the help necessary waveforms.

List out different ad-hoc testing technique for VLSI design.

Compare: Testing and Verification

Explain input scanning algorithm.

Explain equivalence checking.

System Verilog is preferred over other hardware verification languages to implement Test benches in industry. Why?

Explain different functional verification approaches.

Discuss role of verification plan.

What is code coverage? What does 100% code coverage mean?

Design half adder and write it test bench using any hardware description language.1