Testing and Verification — Winter 2025

Differentiate following terms: Testing and Verification

Calculate number of collapsed faults for two input CMOS NOR Gate.

Explain testing methodology for transistor faults in two-input CMOS NAND Gate.

Write the down levels of abstraction in VLSI Testing.

Obtain Controllability and Observability for various signals of 4 inputs AND using SCOAP and Probability based testability analysis.

Explain Muxed-Dfull scan design architecture in detail with necessary waveform.

What is test point insertion? Explain observation point insertion.

Explain the role of Scan Configuration in Scan design flow.

List down Typical Ad hoc DFT techniques.

List down different types of Scan architectures and explain any one in brief.

Draw Concurrent fault simulation flowchart.

What is scan reordering? List and explain different types of it.

Prepare a table showing different design style with Scan design rule and recommended solution.

Explain compile code simulation.

List down different alternative to fault simulation.

Describe parallel fault simulation method with example in detail.

What is convergence model in verification?

Write down importance of assertions in verification.

Explain various timing models.

Explain: black box verification and White box verification

Design half subtractor and write it test bench using any hardware description language

List down different types of simulation models and explain any one of them.

Discuss limitations of linting tools.

System Verilog is preferred over other hardware verification languages to implement Test Benches in industry. Why?

What is code coverage? List down various types of code coverage. Explain any two in detail