Testing and Verification — Summer 2025

Write down challenges in VLSI Testing.

Compare: Testing and Verification.

Define following terms: 1. Equivalent Faults 2. Fault 3. Reject Rate 4. Rule of Ten 5.Fault coverage 6. Defect level 7. Fault detection efficiency

Explain bridging fault models.

Obtain Controllability and Observability for various signals of 5 inputs OR Gate using SCOAP and Probability based testability analysis.

Explain testing methodology for transistor faults in two-input CMOS NAND Gate.

What is mean by scan design rules? Explain scan design rules for following design styles. 1.Derived Clocks 2.Combinational feedback loops

Calculate number of collapsed faults for two inputs CMOS NOR Gate.

Explain input scanning method for logic element evaluation.

Draw and explain Clocked scan cell design with the help necessary waveforms.

What are the advantages of parallel fault simulation? Name the different approaches of it.

Explain toggle coverage and fault sampling.

Draw and explain scan design flow.

Explain logic optimization process for logic simulation.

Draw and explain two pass for nominal event driven strategy.

What is the need of timing models in testing? List down various time models and explain any one of them in detail.

What is the importance and role of verification plan?

Write a VHDL/Verilog code and test bench for 1 X 4 demux.

Draw and explain flowchart indicating steps to do concurrent fault simulation.

What is mean by functional coverage? How it is useful in verification flow?

What is code coverage? Explain its role in verification.

Compare following: White box verification, Black box verification and Grey box verification.

Differentiate between static hazard and dynamic hazard.

Compare Code driven simulation and event driven simulation

Draw and explain verification flow.