Testing and Verification — Winter 2024

Draw flow chart of VLSI development process with mentioning involved testing at each stage.

Define following terms respect to VLSI testing: 1. Yield, 2. Reject rate, 3. Fault coverage and 4. Fault detection efficiency.

Draw two - inputs CMOS NOR gate and write truth table for fault-free circuit and all possible transistor faults. Discuss how to detect all possible transistor faults in this circuit and define and calculate collapse faults.

What is goal of design for testability (DFT) and enlist three basic approaches of DFT.

Define Controllability, observability, testability and testability analysis. Enlist testability analysis techniques.

Write SCOAP combination controllability and observability calculation rules of different logic gates. Find combinational controllability and observability of Half Adder logic circuit at different site using SCOAP analysis techniques.

Derive equation of combinational and sequential controllability and observability of a, b, d, r, CK and q sites for given circuit using SCOAP techniques. rr RReesseett aa dd DD QQ qq bb CCKK

Compare Muxed D, Clocked and LSSD scan cells.

What is scan design rule of derived clock based design and explain it recommended solution with an example.

Enlist three different scan design architecture of DFT. Explain Muxed- Dbased full scan design architecture in detail.1

Draw a flow chart of logic simulation for digital circuit design verification.

Write truth table of four valued logic (0, 1, u, z) 2- inputs AND and OR gates and compare binary logic with four valued logic.

Enlist various algorithms for fault simulation and explain serial fault simulation in detail with algorithm flow chart and example.

Define Transport and Inertial Delay with an example.

Enlist different stages of compile code simulation with its function and draw flow chart of logic levelization.

Define controlling and inversion values of different logic gates (AND, OR, NAND and NOR). Explain input scanning algorithm with flow chart.

What are the advantages of design and verification reuse.

What is test bench? Differentiate: Testing and Verification

What is linting tool? Explain linting verilog source code and limitation of linting tools.

What is assertion? What are the two broad classes of assertion

What are the different approaches of functional verification? Elaborate any one approach.

What is code coverage? And explain it in details. What does 100% code coverage mean?

Enlist purposes of matric as verification tool.

What do you mean by verification intellectual property?

Design 4x1 multiplexer logic design using VHDL/Verilog HDL and write it test bench.