Testing and Verification — Winter 2021

Define (i) Manufacturing process yield, (ii) fault coverage and (iii) Fault detection efficiency

Differentiate following terms: Testing and Verification

Consider the combinational logic circuit in Figure. How many possible single stuck-at faults does this circuit have? How many collapsed single stuck at faults does this circuit have? Determine optimum input test vectors that can detect all single stuck-at faults. a x1 x b d g2 x i y3 e f h c

What is Fault modelling and its requirement?

Discuss all the possible transistor faults in two-input CMOS NOR gate and the method of testing each of them.

What is Mux-Dscan cell design? Explain in detail. Write advantages and disadvantages of Mux-Dscan cell design. Draw level-sensitive muxed-Dscan cell design.

Explain Muxed-Dfull scan design architecture in detail.

Define the terms: (i) Controllability (ii) Observability in context of Design for Testability

Discuss combinational testability analysis by using necessary equations of controllability and observability of different logic gates.

Explain partial scan design. Mention merits and demerits of partial scan design compare to full scan design.

Compare Muxed D , Cloked and LSSD scan cells

What is scan design rule for Derived clock design style and its recommended solution?

Draw and explain scan design flow.1

Differentiate fault simulation and logic simulation.

Enlist Logic element evaluation methods. Draw input scanning algorithm. What is the value of controlling and inversion for the different logic gates?

Draw compile code simulation flow chart and explain all the steps of compile code simulation in detail.

What is Functional Verification?

Enlist different approaches of functional verification and define all.

Explain code coverage in detail.

What is function of linting tools?

Design 4x1 multiplexer and write it test bench using any hardware description language.

Describe simulation based verification method in detail.

What does 100% function coverage mean?

What is mean by assertions in verification and explain implementation assertions and specification assertions.

Draw serial fault simulation algorithm flow chart and explain it with an example.